1 . Field of the Invention
The present invention relates generally to microelectronic circuits, and more particularly, to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) power devices having reduced threshold voltage and high punch-through tolerance formed by the process of impurity concentration compensation.
2. Description of the Related Art
Power semiconductor devices have long been used as replacement for mechanical relays in various applications. Modern day instruments, now built at a miniaturized scale with lower power consumption, require power devices to operate under certain stringent requirements. For instance, in a hand-held cellular telephone or a laptop computer, it is common practice to reduce the main power supply level in order to preserve battery life. Accordingly, power devices suitable to be used in these instruments must be capable of operating under reduced power levels and with low turn-on resistance.
Metal oxide semiconductor field effect transistor (MOSFET) devices using trench gates provide low turn-on resistance and are often used for low power applications. In a trench MOSFET device, the channels are arranged in a vertical manner, instead of horizontally as in most planar configurations. The consequential benefit is the realization of a higher degree of integration on a semiconductor substrate. Furthermore, since the channel directions are vertical, the lateral current paths are basically eliminated. That is, each MOSFET cell assumes its own current path and there are no more shared current paths among cells. Stated differently, the vertical arrangement of the cell channels eliminates a dominant component of the turn-on resistance R.sub.ON, called the junction resistance R.sub.j, in each MOSFET cell inherently built in a planar configuration. The junction resistance R.sub.j originates from the shared current paths among cells in a planar MOSFET device. The shared current paths essentially act as current bottle necks impeding the flow of channel current I.sub.DS and are key contributors to the turn-on resistance R.sub.ON. Elimination of the junction resistance R.sub.j results in reduction in the turn on channel resistance R.sub.ON and consequently curtails ohmic loss during the power-on state of the MOSFET. Lower ohmic loss provides lower power consumption and further alleviates heat dissipation.
FIG. 1 shows a cross-sectional view of a conventional trenched gate MOSFET device having a cell signified by the reference numeral 2. The MOSFET cell 2 includes a trench 4 filled with conductive material 6 separated from the silicon substrate 8 with a thin layer of insulating material 10. There are also other diffusion layers of different impurity types and concentrations deposited in the semiconductor substrate 8. For examples, a source layer 14 is deposited in the body layer 12, which in turn is diffused in an expitaxial layer 18. As arranged, the conductive and insulating materials 6 and 10 in the trench 4 form the gate and gate oxide layer 16, respectively, of the MOSFET. In addition, the depth L measured from the source 14 to the epitaxial layer 18 constitutes the channel length L of the MOSFET cell 2. The epitaxial layer 18 is a part of the drain 20 of the MOSFET cell 2.
When a potential difference is applied across the source 14 and the gate 15, charges are capacitively induced in the body region adjacent to the gate oxide layer 16. The induced charges in essence is an inversion layer and is called the channel 21 of the MOSFET cell 2. When another potential difference is applied across the source 14 and the drain 20, a drain-to-source current I.sub.DS starts to flow from the source 14 to the drain 20 and the MOSFET 2 is said to be at the power-on state.
The conventional trenched MOSFET devices described above have an inherent high threshold voltage V.sub.th, which is normally barely below the main power supply level required in a low power application. For example, in a low power instrument, the power supply V.sub.cc is commonly set at 3 Volts, while the threshold voltage V.sub.th of the MOSFET 2 sits at approximately 2.5 Volts. A turn-on voltage of 3 Volts applied to the gate 15 can hardly turn on the MOSFET device 2. If the power supply is from a battery source, which drops in power supply V.sub.cc level as time progresses, the MOSFET device 2 may never be turned on thereafter. Clearly, the conventional MOSFET 2 is not suitable to be used in applications with reduced V.sub.cc levels. Thus, for the power device to function properly under reduced power supply conditions, the threshold level V.sub.th of the MOSFET 2 has to be correspondingly reduced. Heretofore, various approaches have been attempted to reduce the threshold level of the MOSFET 2 but have not been proved successful.
Referring to FIG. 1, the threshold voltage V.sub.th is defined as the minimal potential difference between the gate 15 and the source 14 required to barely induce the channel 21 in the body layer 12. The threshold voltage V.sub.th is dependent upon a variety of factors including, inter alia, the thickness of the gate oxide 16, and the impurity concentration of the body region 12. The gate oxide thickness and the impurity concentration of the body region are more accessible parameters for adjustment, in contrast with other parameters such as the work functions or the Fermi levels of the basic materials of the MOSFET 2, which parameters require higher degree of difficulty to manipulate. A precise mathematical expression for the threshold voltage V.sub.th can be found in a publication by Wolf et al., "Silicon Processing for the VLSI Era", Lattice Press, IEEE Transactions on Electron Devices, Vol. 2, page 301.
Very often, the thickness of the gate oxide 16 is reduced to lower the threshold voltage V.sub.th. However, the drawback with this approach is that making the gate oxide thickness thinner seriously undercut the final production yield and furthermore the reliability of the MOSFET. As is shown in FIG. 1, the thinner the gate oxide layer 16, the higher the probability of the conductive material 6 short-circuiting the other layers in the semiconductor substrate 8 through oxide defect in the gate oxide layer 16.
The second approach to reduce the threshold voltage V.sub.th is to lower the impurity concentration of the body layer 12. However, results of this approach is also fraught with various problems.
FIG. 2 shows the diffusion profile of the MOSFET cell 2. The abscissa axis of FIG. 2 represents the distance measured from the planar surface 22 toward the substrate 8 (FIG. 1). The ordinate axis of FIG. 2 corresponds to the impurity concentration of the various layers in absolute value. For example, the source layer 14 is located at a distance of x=x.sub.js from the planar surface 22. Similarly, the body layer 12 is positioned at a distance from x=x.sub.js to x=.sub.jb.
During normal operation, the drain 20 and the body layer 12 are reversely biased. Consequently, a depletion layer is formed characterized by a depletion region 24 with a depletion width W as shown in FIG. 1, in which the depletion layer 24 is partly shown in hidden lines. As is well known in the art, the lighter the impurity concentration of a layer, the wider is the depletion width W extending into that layer. Referring back to FIG. 1, if the body layer 12 is too lightly doped, the depletion layer 24 may encroach into the source layer 14 resulting in an undesirable effect called "punch-through". During punch-through, breakdown ensures in which drain-to-source current I.sub.DS flows directly from the source 14 to the drain 20 without passing through the channel 21. Specifically, as shown in FIG. 2, the hatched area underneath the impurity curve from x=x.sub.js to x=x.sub.jb corresponds to the total charge stored in the body layer 12. The threshold voltage V.sub.th of the MOSFET cell 2 can be lowered by reducing the impurity concentration of the body region 12, as is graphically shown by the lowered curve 26 shown in hidden line in FIG. 2. It should be noted that the ordinate axis of FIG. 2 is in logarithm scale. A slight shift in the curve 26 corresponds to a substantial change in total charge. The lowering of the impurity concentration in the body layer 12 entails the widening of the depletion layer 24 and increases the possibility of the MOSFET 2 running into punch-through as described above.
There have also been attempts to diffuse the source region 14 to a deeper depth, as shown in FIG. 2 by another hidden line curve 28 intersecting with the original body diffusion curve 30 to form a new source junction at x=x.sub.js. The purpose is to reduce the total charge stored in the body layer 12. However, the encroachment problem of the depletion region 24 remains more or less the same because this time, the depletion layer 24 needs only to travel a shorter distance to reach punch-through.
Portable instruments and hand-held electronic products operated by batteries are now in high demand. These instruments and products are all operated by batteries with limited battery lives, at least until the next battery recharges. To preserve battery power and to ensure reliability, there has been a long-felt and increasing need to provide power devices capable of operating under reduced power levels and with low turn-on resistances, yet with robustness in punch-through tolerance.